Verilog 学习笔记

Syntax

By default, Verilog simulators treat numbers as decimals.

4'hA = 4'd10 = 4'b1010 = 4'o12	// Decimal 10 can be represented in any of the four formats
8'd234 = 8'D234                 // Legal to use either lower case or upper case for base format
32'hFACE_47B2;                  // Underscore (_) can be used to separate 16 bit numbers for readability

Numbers without a base_format specification are decimal numbers by default. Numbers without a size specification have a default number of bits depending on the type of simulator and machine.

integer a = 5423;       // base format is not specified, a gets a decimal value of 5423
integer a = 'h1AD7;     // size is not specified, because a is int (32 bits) value stored in a = 32'h0000_1AD7

A sequence of characters enclosed in a double quote " " is called a string. It cannot be split into multiple lines and every character in the string take 1-byte to be stored.

"Hello World!"        // String with 12 characters -> require 12 bytes
"x + z"               // String with 5 characters

"How are you
feeling today ?"      // Illegal for a string to be split into multiple lines

Data Types

There are different types of nets each with different characteristics, but the most popular and widely used net in digital designs is of type wire.

It is illegal to redeclare a name already declared by a net, parameter or variable as shown in the code below.

module design;
	wire    abc;
	wire 	a;
	wire 	b;
	wire 	c;

	wire    abc;   // Error: Identifier "abc" previously declared

	assign abc = a & b | c;
endmodule

An integer is a general purpose variable of 32-bits

integer     count;              // Count is an integer value > 0

Verilog data-type reg can be used to model hardware registers since it can hold values between assignments. Note that a reg need not always represent a flip-flop because it can also be used to represent combinational logic.

A time variable is unsigned, 64-bits wide and can be used to store simulation time quantities for debugging purposes. A realtime variable simply stores time as a floating point quantity.

time        end_time;           // end_time can be stored a time value like 50ns
realtime    rtime;              // rtime = 40.25ps

Scalar and Vector

A net or reg declaration without a range specification is considered 1-bit wide and is a scalar. If a range is specified, then the net or reg becomes a multibit entity known as a vector.

wire 	    o_nor;           // single bit scalar net
wire [7:0]  o_flop;          // 8-bit vector net
reg         parity;          // single bit scalar variable
reg  [31:0] addr;            // 32 bit vector variable to store address